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Success

TSMC

"With Rubix, Azuro continues its track record of strong technology innovation to help close the design productivity gap. Rubix increases clock frequency and reduces leakage power on our hardened CPU cores. And it does this without any change in sign-off methodology."

July 7, 2010

S. T. Juang

Senior Director of Design Infrastructure Marketing, TSMC

Sondrel

"We are very experienced users of Azuro's software and by adding PowerCentric to our Helium flow, we are able to offer our customers significant reductions in dynamic power and accelerated turnaround time on complex system-on-a-chip designs. When it comes to clock tree synthesis, Azuro is the clear industry leader."

March 30, 2010

Graham Curren

CEO, Sondrel

TSMC

"Rising design setup costs and design cycle times are critical challenges for the semiconductor industry. The TSMC Integrated Sign-Off Flow brings together parties across the entire chip design ecosystem into a tightly controlled fully automated platform for achieving best in class silicon quickly and with lowest cost."

April 28, 2009

S.T. Juang

Senior Director of Design Infrastructure Marketing, TSMC

Newport Media, Inc.

"It typically took us several days and three or more manual iterations to get the clock right. With Azuro we are able to run a one-step automatic script that produces a much better clock result in about one hour."

March 24, 2009

Darren Woodhouse

Physical Design Manager, Newport Media, Inc.

NVidia

"Clock concurrent optimization makes sense. Rubix plugged easily into our flow, and improved key chip speed metrics (WNS and TNS) out of the box on some of our toughest blocks with no impact on area. We view clock concurrent optimization as a key evolutionary step in backend physical design."

February 25, 2009

David Dumoulin

Director of Engineering, NVIDIA

TSMC

"The increase in design complexity and the demand for low power highlights clock implementation as an emerging bottleneck for design performance and designer productivity. Azuro’s PowerCentric tool delivers significant power savings, and improves clock timing by reducing clock skew and insertion delay."

June 4, 2008

S.T. Juang

Senior Director of Design Infrastructure Marketing, TSMC

Ikanos

"Our customers' power requirements push the limits of cooling and power supply, so reducing power consumption is a critical issue for these applications. We adopted PowerCentric in order to maintain our leadership in delivering low power solutions to our customers."

February 27, 2008

Ravi Selvaraj

Vice President of Product Development, Ikanos Communications

Atheros

"Clock tree synthesis is a critical step in the design flow which the EDA industry has under-invested in for some time now. Azuro's PowerCentric truly is a fresh approach to CTS, and enables us to deliver silicon to market faster and with even lower power consumption than before."

"Using Azuro's PowerCentric, Atheros has been able to improve the quality of our clock trees. This increased ability to manage clock distribution has contributed to the low power dissipation of our mobile and client products."

January 28, 2008

Steve Padnos

Methodology Architect, Atheros

STARC

"PowerCentric was able to greatly reduce dynamic clock power by finding many more clock-gating opportunities and building much more efficient clock trees. Azuro’s results are especially impressive because they are more efficient across the board. The low-power result also achieved a better clock skew, a shorter insertion delay, and reduced total buffer area."

November 9, 2007

Nobuyuki Nishiguchi

Vice President of the Design Methodology Group, STARC

NVidia

"For NVIDIA, we must deliver unmatched features and performance in our graphics, multi-media communication processors and application processors while meeting tight power budgets, performance and area constraints. Consequently, our designs contain extremely complex clock trees with multiple branches at the block level that also needs to be balanced for min./max. corners. PowerCentric gives us the ability to implement superior clock trees inside our existing physical framework of EDA tools."

May 31, 2007

David Dumoulin

Director of Engineering, NVIDIA

Toshiba

"Power has become one of the critical drivers for TAEC customers. In our evaluation, PowerCentric delivered 15 to 25 percent reduction in power consumption compared to our existing implementation with minimum impact on design size or performance. Since many of our customers have designs that sit on the cusp of a power/performance envelope, this power reduction could make possible an array of low-cost, package solutions.

"PowerCentric integrates smoothly into our low-power design flow as an alternative to our current clock tree synthesis capability. In addition to its power reduction benefits, the product also offers extensive features to analyze our clock trees and power dissipation, which we believe will significantly enhance the productivity of our engineers on designs containing complex clock topologies."

May 31, 2007

Atsushi Watanabe

Vice President Design Solutions, TAEC

Arc

"ARC continuously strives to offer best-in-class configurable solutions that fit the stringent needs of customers designing SoCs for power sensitive applications. By leveraging Azuro’s PowerCentric low power methodology, licensees can further reduce power consumption of ARC’s configurable subsystems and processors by more than 20% without impacting processor footprint."

July 19, 2006

Peter Hutton

Senior Vice President of Engineering, ARC International

CSR

"Low power is a key driver for CSR. PowerCentric fits seamlessly into our design flow and has enabled us to achieve significant reductions in the digital power consumption of our chips."

June 13, 2006

James Collier

Co-founder and Chief Technology Officer, CSR

Broadcom

"Power dissipation has become increasingly important to the semiconductor industry as consumers demand ever more talk time, play time, and functionality in their next-generation mobile phones and portable devices. Meeting power requirements is one of the biggest challenges facing chip design teams today. Without effective clock gating, most of the active power in a typical digital logic block is consumed by the clock and registers. Azuro provided Broadcom with design automation tools that assisted in reducing the active power consumption of our BCM2702 mobile multimedia processor."

May 16, 2005

Steve Barlow

Senior Director of Engineering, Mobile Multimedia Products, Broadcom